parallel input serial output shift register vhdl code

I am designing a universal shift register of 4 bits in VHDL. This means that maybe something like this is a good idea: Okay, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. TYPE POSSIBLE_STATES IS (waiting, shifting) Perhaps a wait state for when the process is not shifting, and a shifting state for when it is. Next it might be a good idea to think of the states your process will be in. Keeps track of how many iterations (or shifts) have occurred so far. You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of theĪ process is triggered every time one of the signals on the This allows for s_in to be shifted out of s_out ever clock cycle. What you really want is a loop where each iteration occurs on a new clock edge. The entire loop is executing in a single clock cycle. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. Temp_reg <= s_in & temp_reg(n-1 downto 1) Signal temp_reg: std_logic_vector(n-1 downto 0) := (Others => '0') Parallel_in: in std_logic_vector(n-1 downto 0) I don't think the for loop is working, as the shifting is not restricted to n times.

I've put a for loop to shift n times inside a process.

When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low.

Parallel input serial output shift register vhdl code